1. Field of the Invention
The present invention relates to a digital TV receiver such as an HDTV(High Definition Television) receiver, and more particularly, to a device and method for generating a clock in an HDTV receiver.
2. Discussion of the Related Art
In order to fix standards for HDTV broadcasting, various steps have been taken recently to organize the Grand Alliance ("GA") in the U.S. and to finalize HDTV standards. While each of the existing video standards has an independent, single video format standard, the GA video standard accommodates many kinds of video formats, and is not limited to a single video format. In other words, in the digital television system, the GA format can accommodate video transmissions from various sources. For example, the transmitter can transmit video signals at a mix of 59.9 Hz and 60 Hz video frame rates(or display rates) in 27 MHz reference frequency. For restoring the clock signal at the receiver side, display clock signals should be changed to match the transmitted 59.9 Hz or 60 Hz video frame rates. Accordingly, the receiver side is required to have clock signals of different sampling frequencies for the different video formats, each of those clock signals should be in agreement with the clock signal used on the transmitter side, i.e., in the encoder, or their line frequencies or field or frame frequencies should be in agreement, exactly. As explained, all digital television sets require a device for restoring clock signals without fail, which can appropriately change the present clock signal into a clock signal in agreement with the display format. If the restoration of the clock signal is not perfect, an overall picture quality will be degraded.
Therefore, a conventional HDTV clock generating device restores the clock signal transmitted from the transmitter by way of time restoration in which the receiver at first restores the transmitted data loaded on a carrier according to each of the video formats transmitted from the transmitter. And, a restored clock signal is passed through a PLL(Phase Locked Loop) to generate a desired frequency.
The aforementioned conventional PLL will be explained with reference to the block diagram shown in FIG. 1. A conventional clock generating device in an HDTV receiver includes local oscillators 13a and 13b for respectively generating clock signals of different frequencies, a 1/1000 frequency divider 14a for dividing the frequency of the clock signal from the local oscillator 13a by 1/1000, a 1/1001 frequency divider 14b for dividing the frequency of the clock signal from the local oscillator 13b by 1/1001, a phase error detector 11 for receiving a reference clock signal and the clock signal 1/1000 or 1/1001 divided of the clock signals from the local oscillator 13a and 13b and comparing the clock signals with the reference clock signals to detect a phase error signal, a loop filter 12 for converting the phase error signal from the phase error detector 11 into a signal voltage for controlling the local oscillators 13a and 13b, a first selector 15a for selecting one from the local oscillators 13a and 13b in providing the control signal from the loop filter 12 depending on a video format of a received video signal, a second selector 15b for selecting one from the 1/1000 frequency divider 14a and 1/1001 frequency divider 14b in providing the 1/1000 or 1/1001 divider clock signal to the phase error detector 11 depending on a video format of a received video signal, a divider for system clock generating 16 for dividing outputs from the local oscillator 13a and 13b controlled by the control voltage from the loop filter 12 in generating a system clock signal, and a third selector 15c for selecting one from the outputs of the local oscillators 13a and 13b depending on the video format of the received video signal in providing one of the outputs to the divider for system clock generating 16.
If the frame rate of the conventional clock generating device in an HDTV receiver is 59.9 Hz, the local oscillator 13a generates a frequency signal of 4788 fH when the sampling frequency is 4788 fH, which is 1/1000 divided in the 1/1000 divider 14a to generate a frequency signal of 4.788 fH, identical to the reference clock signal. The local oscillator 13b generates a clock signal of 4788.times.(1001/1000), which is then 1/1001 divided in the 1/1001 divider 14b also to generate a frequency signal of 4.788 fh, identical to the reference clock signal, too. Thus, the selector 15c is used in selecting one clock signal from the two clock signals of the two local oscillators 13a and 13b depending on the video format of the received video signal. That is, when the video format of the received video signal has a frame rate of 59.94 Hz or 29.97 Hz, the selector 15c selects a signal from the local oscillator 13a, and when the video format of the received video signal has a frame rate of 30 Hz or 60 Hz, the selector 15c selects a signal from the local oscillator 13b. This selected clock signal can be used as a system clock signal after being demultiplied by the divider for system clock generating 16.
By adding conventional switching functions to the conventional PLL circuit, the conventional clock generating device in an HDTV receiver selectively restores a clock signal corresponding to a video format of a received video signal. In other words, the conventional clock generating device selects a suitable clock signal from the PLL circuit by switching between the local oscillators and dividers in the PLL and uses the selected clock signal as a system clock signal. However, the conventional clock generating device in an HDTV receiver has a problem in that the clock signal becomes unstable when the switch in the PLL is changed over. That is, because there happens a change of clock signal to a clock signal having a different frequency regardless of the immediately proceeding clock signal upon switching in the PLL, an error can be occurred in a switching section, and further a degradation of product reliability may be caused due to unstable subsequent process. Moreover, though there have been many suggestions on arts for generating a clock signal, there has been no suggestion on art for changing a clock signal depending on a frame rate of a video signal, i.e., video format. In the aforementioned digital television system, it is difficult to change a clock signal by means of the conventional art which uses a PLL. Eventually, when there is only one display clock signal in a transmitted broadcasting program, the display clock signal can be restored easily by using the conventional PLL, but exact restoration of display clock signals of different frequencies has been difficult.